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Aurix/Tricore实验分享之六十五:Tricore 1.3内核整数除法研究

Aurix/Tricore实验分享之六十五:Tricore 1.3内核整数除法研究

User12775
Level 5
Level 5
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比较让人吃惊的一点就是:


Tricore 1.3.1内核没有单条整数除法指令. 要完成整数除法, 需要调用多条指令来完成运算.


架构文档中的说明是:


Division of 32-bit by 32-bit integers is supported for both signed and unsigned integers.
Because an atomic divide instruction would require an excessive number of cycles to
execute, a divide-step sequence is used, which keeps interrupt latency down. The divide
step sequence allows the divide time to be proportional to the number of significant
quotient bits expected.
The sequence begins with a Divide-Initialize instruction: DVINIT(.U), DVINIT.H(U) or
DVINIT.B(U), depending on the size of the quotient and on whether the operands are to
be treated as signed or unsigned. The divide initialization instruction extends the 32-bit
dividend to 64-bits, then shifts it left by 0, 16 or 24-bits. It simultaneously shifts in that
many copies of the quotient sign bit to the low-order bit positions. 4, 2 or 1 Divide-Step
instructions (DVSTEP or DVSTEP.U) then follow. Each Divide-Step instruction develops
eight bits of quotient.
At the end of the divide step sequence, the 32-bit quotient occupies the low-order word
of the 64-bit dividend register pair, and the remainder is held in the high-order word. If
the divide operation was signed, the Divide-Adjust instruction (DVADJ) is required to
perform a final adjustment of negative values. If the dividend and the divisor are both
known to be positive, the DVADJ instruction can be omitted.


意思是: 如果使用单条整数除法指令, 中断延迟会被影响. 把整数除法拆成几条指令, 则每条指令都可以被中断,从而解决了这个问题.


值的注意的是, 对于浮点数, 是有单条除法指令的.


而且在TC1.6版本中, 又增加了单指令的整数除法指令供用户选择使用多指令还是单指令来完成整数除法.


不管怎样在Tricore 1.3.1内核或更早的版本中, 要做整数除法,只能使用多条指令来完成运算. 下面以一个例子来说明具体的做法.

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