英飞凌大中华区技术专家FAQ大总结
1. Q: 为啥需要nvSRAM?
A: nvSRAM can be used in applications that require fast read and write access times and also requiring the memory to be non-volatile (the information retained even when power is turned off). Memories such as EPROMs,
EEPROMs, and Flash are also non-volatile, but the write and erase times are far too slow for normal system operation. nvSRAM product is advantageous over others since it offers the convenience of SRAM operation with the Non-Volatile features.
2. Q: 英飞凌会提供 nvSRAM 那些产品组合？
A: a). nvSRAM without RTC (Real-Time- Clock) Parallel – Densities: 16Kbit through 8Mbit, Serial – Density: 1 Mbit, SPI interface
b). nvSRAM with RTC Parallel – Densities: 256Kbit, 1Mbit and 4 Mbit. Serial – Density: 1 Mbit, SPI interface
3. Q: RTC 是什么哪里会使用到RTC 功能
A: RTC device is one that maintains a digital image of the Time-Of-Day (TOD) or calendar. It is used in applications such as POS (Point-Of-Sale) terminal, server applications etc. where the critical information is saved with time-tagging.
4. Q: nvSRAM 主要的应用有那些
A: nvSRAM is a perfect fit for applications requiring high speed, nonvolatile memory. Its ease of insertion makes it a natural choice where batteries and other nonstandard packaging concerns rule out other technologies. Its high speed allows it to operate where other technologies (BBSRAM, Flash, EEPROM) can’t, such as embedded DSP and other fast processor applications. It provides secure data retention such as found in financial, and gaming industries because of long data retention times. Ex: Digital Oscilloscopes, Hubs and Routers, Gaming, Servers, RAID (Redundant Array of Independent Drives), PLCs and POS
5. Q: nvSRAM 的读写性能如何？
A: Read/Write operation in nvSRAM is performed on the SRAM during power supply is on. At power down, the contents of SRAM are copied into non-volatile EEPROM cell of nvSRAM immediately in order to prevent data loss, and no access is allowed with SRAM at this time. The copied data is later recovered from EEPROM into SRAM during power-up.
6. Q: nvSRAM 自动存储/硬件存储/软件存储是怎么实现的？
A: When the system Vcc drops below VSWITCH (typically 2.65V for 3V parts and 4.4V for 5V parts), the entire SRAM array is stored in parallel into EEPROM within time duration of less than 8 milliseconds.
If the HSB# (Hardware Store Busy) pin in nvSRAM is asserted low, a STORE operation will be initiated immediately after completing the current cycle. This is called a Hardware STORE operation.
In case of Software STORE operation, the STORE operation is initiated by reading a specific sequence of six addresses in order, with no intervening access to other locations.
The nvSRAM is unavailable for the normal access during STORE cycle initiated by any of the three means.
